Basic Hardware

Main memory and registers belonging to each processing core, are the only general-purpose storage that the CPU can access directly.

• Machine instructions can have memory addresses as an operand, but not disk addresses.

Remember that RISC systems are load/store, and do not directly access memory. Instead, content is loaded from a memory location, into a register.

• Registers are the fastest storage in the memory hierarchy; CPU's can access register in one cycle. Some CPUs are capable of decoding instructions and performing operations at the rate of 1+ operations/clock tick.

Main Memory is accessed using a transaction bus, making it a slower access tier of the memory hierarchy compared the registers. CPUs may take many CPU cycles to complete a memory access.

• CPU would have to stall the pipeline. [See 1, 2]

• Necessitates the use of Cache. A multicore architecture design will typically include a private L1 and L2 Data cache (and L1 instruction cache if non-unified); each core would share an LLC (Last-level Cache), typically L3. [See SRAM cache]

Memory Protection

Memory space must be protected. When a system first boots, it boots to read-mode, a 16-bit OS mode that provides no memory protection. Most bootloaders will attempt to switch to protected mode as soon as possible.

An Operating System must protect kernel space from user-space processes, as well as protecting a user-space process from other user processes. Since the operating system rarely intervenes between CPU and its memory accesses, the hardware must provide this protection.

Separate Per-process Memory

Each process should have it own address space for operation. This is necessary for concurrent execution on an operating system, and is a fundamental step in protecting user processes from one another.

Base and Limit Registers

Base and limit registers are used to define the range of legal addresses that a process may access. The base register hold the smallest legal physical address, while the limit register specifies the size of the range.

Note: Don't confuse this with base/limit shown in Global Descriptor Table to learn more.

The base and limit register can only be set using a privileged instruction, inherently restricted use to the operating system (which runs in kernel space).

Any attempt by a user-space program to access kernel space memory, or another processes memory will result in a trap. The exception will subsequently be handled by the processor, co-processor, or programmable interrupt controller.

The Kernel Exception

The kernel, however, is permitted to access privileged memory space, as well as user memory space. This allows it to load and unload user programs.

• Consider a context switch in a multiprocessing system. The kernel can store a processes state in main memory, freeing up registers for another process. (In some cases, a process is responsible for saving its own state).

Excellent Resources

• Multi-core and multi-threading Blog post.

• Micoprocessor Design Wiki

  • The page on cache is relevant to this post.

A multithreaded core can switch from the stalled hardware thread to another hardware thread.