typically able to process one of the operands using barrel-shifter
if the 'S' suffix is used on a data processing instruction, it updates the flags in the cpsr.
syntax: {}{S} Rd, N
Example Let: r5 = 5 r7 = 8
MOV r7, r5
AFTER: r5 = 5 r7 = 5
Barrel Shifter - Remember the Syntax: {}{S} Rd, N
- Given the syntax above, N can be a register Rm that has been preprocessed by the barrel shifter prior to beng used by a data processing instruction
- DP instructions are processed within the ALU
- ARM can shift the 32-bit binary pattrn in one of the source registers left or right by a specific number of positions before it enters the ALU
- this increases the flexibility and power of many data processing operations
- Some instructions like MUL, CLZ (count leading zeros), and QADD (32-bit add) do not use the barrel shift.
- this allows for fast multiplies or division by power of 2
- Barrel shifter operations:
- LSL logical shift left
- LSR logical shift right
- ASR arithmetic shift right
- ROR rotate right
- RRX rotate right extended
- Example (note: LSL logical shift left)
Let:
r5 = 5
r7 = 8
MOV r7, r5, LSL #2
AFTER:
r5 = 5
r7 = 20
// left shift 1 bit is the same as multiplying by 2. r5 << 2 is like r5 * 4
- Barrel shift operations syntax for DP instructions
- Immediate
#immediate
- Register
Rm
- Logical Shift left by immediate
Rm, LSL #shift_imm
- Logical shift left by register
Rm, LSL Rs
*** repeated for other barrel shifter options ***
- Example:
cpsr = nzcvqiFt_USER
r0 = 0x00000000
r1 = 0x80000004
MOVS r0, r1, LSL #1
cpsr = nzCvqiFt_USER
r0 = 0x00000000
r1 = 0x80000004
MOVS r1 into r0, but first the barrel shifter will left shift by 1 (multiply the current value in r1 by 2)
- the suffix 'S' changes the cpsr, for the instruction MOV, the condition that would be changed is C or Carry.