ARM Registers
Load-Store Architecture
load -> copies data from memory to registers in core
store -> copies data from registers to memory
Data items are placed in a register file
storage bank consisting of 32-bit registers
ARM core is 32-bits
instructions treat registers as holding signed/unsigned 32-bit values
signed converts 8-bit and 16-bit numbers to 32-bit values when read from mem and placed in reg.
Source Registers
Rn and Rm
Rm can be preprocessed in the barrel shifter before entering ALU
ALU and Barrell shifter can calculate a wide range of expressions and addresses
Destination Register
Rd
Source operands are read from register file uinsg internal buses A and B
Load and store instructions use the ALU to generate an address
This address will be held in register and broadcast on the address bus
Overview: - Load from Data - Sign extend - Store in register file (r0 - r15) - operands read from register file and placed in Rn and Rm - Using bus A and B, Rn and Rm are moved to the ALU for the operation - Rm can be preprocessed in barell-shifter to calc addresses and expressions - ALU and or MAC () get register values Rn and Rm from Bus A and B - Result is stored in Rd via bus - Broadcast ALU computed address on BUS - Result in Rn is written to Register file via result bus - Incrementer updates the address register before core reads/writes next register value - continue processing until interrupt or exception
General-Purpose Registers - r0 - r15 - r13 = sp - r14 = lr - r15 = pc
Typically runs in user mode, 7 different modes exists
protected mode commonly used when executing applications
18 active registers
16 data registers (visible to programmer)
r0 - r15
r13 -> stack pointer (sp) and stores head of the stack
r14 -> link register (lr) where the core puts the return address when calling a subroutine
r15 -> program counter (pc), address of next instruction
r13 and r14 can be used as GP registers.
dangerous to use r13 as GP when running an Operating System
OS's assume r13 is the stack pointer
r0 - r13 are orthoganal (whatever you can do to one, you can do to any other).
2 processor status registers
Current Program Status Register
Used to monitor and control internal operations
8-bit Fields: flags, status, extension, control
extension/status -> future expansion
control field -> processor mode, state, interrupt mask bits
flag field -> condition flags
Save Program Status Register
same format, but saved (default) state
Processor Modes
determines which registers are active and have access to cpsr
privileged mode -> Full read/write to CPSR
non-priv -> read only to control field but write to condition flags
6 privileged modes
abort, fast interrupt request, interrupt request, supervisor, system, undefined
System is a privileged version of user mode allowing full read/write
non-priv
user mode
*(lookup binary for each mode in Book)
Modes maskings
Abort (10111)
Fast interrupt req (10001)
Interrupt req (10010)
Supervisor (10011)
System (11111)
User (10000)
Banked registers
only available during certain state e.g. abort mode -> r13 and r14_abt and spsr_abt
Every mode except user can change the processor mode
write bits to mode field in CPSR
State and ISA
ARM ISA only active when processor is in ARM state
THUMB ISA only active when processor is in THUMB state
in this state, only executing 16-bit instructions
cannot intermingle ARM, THUMB, and Jazelle instructions
Jazelle ISA
8-bit ISA that is a mix b/t hardware and software to speed up JAVA bytecodes
CPSR
J and T bits (jazelle and thumb) reflect the state of processor
If (J == 0 and T == 0); ARM state and execs ARM instructions
Core executes a branch instruction to change states
Interrupt Mask - prevent specific interrupt rquests from interrupting the processor - Interrupt Levels in ARM: IRQ and FIQ - interrupt request - fast interrupt request - the two bits field in the CPSR - named: iF - 0 or unset, means the interrupts are masked - e.g. |0|1| i F - The above would show that IRQ interrupts are masked - FIQ should almost never be masked, these are important for protecting against side-channel attacks and cache-timing attacks - e.g. memory access attempt to kernal space would be an FIQ interrupt and should not be masked. Condition Flags: - Q -> saturation (overflow and saturation) - V -> oVerflow (signed overflow) - C -> Carry (unsigned carry) - Z -> Zero (result is zero, equality tests) - N -> Negative (bit 31 of result is a binary 1)
Conditional Execution
Controls if the core will execute an instruction
Processor compares the condition attribute with the condition flags in cpsr
if match, instruction is executed
condition attribute is postfixed in the instruction mnemonic (encoded into instruction)