Load/Store Instructions

• Load / Store instructions

  • used to move data from memory into a register, and from a register to memory

  • 3 Types of load-store instructions

    • single-register transfer

    • multiple-register transfer

    • swap

• Single register transfer

  • moving a single data item in/out of a register

    • example: LDR / STR

  • can only operate on a boundary alignment that is the same as the datatype size being loaded/stored.

    • e.g. a 32-bit word can only be loaded on a mem address that is a multiple of 0, 4, 8, 16, and so on.

  • example (load register r0 with contents of memory address pointed to by reg r1)

    LDR r0, [r1] ; Can also be LDR r0, [r1, #0] STR r0, [r1] ; Can also be STR r0, [r1, #0]

  • Addressing Modes: Data Base Address Example

• Preindex with writeback: mem[base + offset] base + offset LDR r0, [r1,#4]!

• preindex mem[base + offset] not updated LDR r0, [r1, #4]

• postindex mem[base] base + offset LDR r0, [r1], #4

• predindex with w/b calculates an address from base register plus offset and updates that address base register with new addr.

  • the '!' denotes update, so given: LDR r0, [r1, #4]!

  • r1 is the base register, #4 is the offset, and '!' means update r1 with the calculated address (base + offset)

    • remember enclosing in [ ] means memory calculation. [base, #offset] is calculate memory address as address of base + offset.

• preindex is similar to preindex with w/b, except it does not update base with the newly calculated addr.

• postfix only updates address base register after the address is used

• Addressing mode combinations

  • note: Rn is source register, but it is not the source register Rm that can be preprocessed by the barrel shifter

  • some modes use Rn others use Rm

preindex with immediate offset [Rn, #+/-offset_12] predindex register offset [Rn, +/-Rm] Preindex with scaled register offset [Rn, +/-Rm, shift #shift_immediate] ... repeat patterns above for preindex and postindex

• Multiple-register transfer

  • can transfer multiple registers b/t memory and the processor in a single instruction