ARM Design Philosophy
Physical features
embedded systems require battery power
ARM is designed to be small to reduce power consumption and extend battery operation
High code density is another major require
embedded systems have limited memory due to cost and/or size restrictions
high code density is useful for apps that have limited on-board memory, e.g. mobile devices or mass storage
ARM has incorporated hardware debug tech, allowing engineers to view what is happening while the processor executing code
ARM core is not pure RISC because of the constriants of embedded systems
often viewed positively bc ARM doesn't take RISC concepts too far.
Variable cycle execution for certain instructions - Not all ARM instructions execute in one cycle - load-store-multiple instructions vary in number of cycles, which depends on number of registers transferred - Transfers can occur in sequential memory addresses - increases performnace -> sequenctial access is faster than random - code density is also improved since multiple register transfers are common at beginning/end of function
Code density (Also called: byte efficiency, code efficiency, operation length reduction) - refers to all of the instructions needed to completed a particular task - whether or not the majority of instructions fit into instruction cache, has major implications on performance - CISC introduced more powerful instructions to the ISA, requiring fewer total instructions required to complete common tasks - This generally improved code density - RISC saught to eliminate complex instructions by breaking them into simple ones that can exec in 1 cycle - RISC prioritized other CPU performance metrics over code density - Because CISC uses Variable length instructions (variable-length opcode) commonly used instructions should be short - analogous to the 80/20 rule - a small number of instructions from the ISA are used for the majority of a workload. - RISC uses fixed-length (or fixed-width) instructions. It's known that 16-bit optimizes code density for fixed-width instructions, compared to 8 and 32-bit width
Inline barrel shifter
(hardware component) preprocesses one of the input registers before it is used by an instruction
improves core performance and code density by expanding the cability of many instructions
SEE ch 2, 3, 4 (ARM System Developer's Guide)
*** VERY IMPORTANT ***
THUMB ISA
16-bit fixed length ISA
An enhancement to preprocessor core
an addition the the original ISA
Permits ARM core to execute 16 or 32-bit instructions
30% optimization to code density
Conditional execution
instruction only executed when specific condition is met
Enchanced instructions
DSP (digital signal processor) instructions
allows faster-performing ARM processor in cases permitting the replacement of traditional combinations of processor + DSP
supports 16x16-bit multiplier operations and saturation