RISC Review

RISC Design Philosophy

• RISC's design philosophy is aimed at delivering simple but powerful instructions that execute within a single cycle @high clock speed

  • Reduce complexity of instructions, places greater demand on the compiler (software) rather than hardware

    • software has more flexibility

• Instructions

  • Fixed-length instructions, allowing future instructions to be executed before decoding current instructions

    • CISC instructions are variable-length

  • RISC has a reduced number of instruction classes, each class proivded simple instructions that exec in 1 cycle

    • Complex instructions are broken up in to simple ones

      • i.e. divide

• Pipelines

  • Uses a pipline for parallel execution. Instructions can be executed in the pipeline

    • CISC requires the use of a miniprogram called microcode to execute instructions

  • Registers

    • RISC uses large general-purpose register set

      • each register can hold an address or data

      • registers are fast local stores

• Load-Store (register-to-register) Arch

  • operations are only performed on data in registers

  • Load and store instructions are used to move data into registers

  • Separate Load and store instructions are used to move data from register bank to external mem

    • separating memory access from data processing provides an advantage

      • data items are held in the register bank and can be used multiple times. No need to for multiple memory accesses

      • Memory access can be costly

        • Remember hierarchy and cycle latency, hit miss, invalidation, coherency, etc.

RISC -> greater complexity on the compiler, less on the hardware CISC -> greater complexity on the hardware, less on the compiler