Maurice's Notes
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Low Level Computing
Low Level Computing
  • Operating Systems
    • General Operating Systems
      • OS Structure
      • Main Memory
        • Basic Hardware
        • Address Binding
        • Memory Address Register
      • Booting
        • MBR (Master Boot Record)
        • Global Descriptor Table
      • Direct Memory Access (DMA)
        • DMA
      • Processes
        • Basics
        • Process Scheduling
    • Linux Operating System
      • Linker Scripts
      • Position Independent Code/Executable
      • Relocation
      • Understanding PLT and GOT
    • Windows Operating System
      • Page 1
    • Real-Time Embedded Systems
      • Real-Time Scheduling
        • Cyclic Executive
  • Computer Architecture
    • Architecture Fundamentals
      • Introduction
      • Cache Basics
      • Cache Memory
      • A Few CPU Formulas
    • RISC Architectures
      • ARM
        • ARM Design Philosophy
        • RISC Review
        • Exceptions, Interrupts, & Vector Table
        • ARM Pipelines
        • ARM Registers
        • ARM Branch Instructions
        • ARM CSPR (Instructions)
        • ARM Data Processing Instructions
        • Load/Store Instructions
        • Profiling Cycle Counter
        • Compiler Optimizations
      • RISCV
    • CISC Architectures
    • Cache Coherency
      • Basic Introduction
      • Memory Sequential Consistency
  • Exploits
    • Walkthrough: Return-to-Libc
    • Access Physical Memory
  • Compilers & Runtime Systems
    • Introduction
      • Programming Language Basics
      • Static Scope
    • Syntax Translation
      • Syntax Defined
      • Parsing
    • Algorithms
      • FIRST FOLLOW (Top-Down) Parsing
      • Building a Recursive Descent Parser
      • Construction: Regular Expression -> NFA
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  1. Computer Architecture
  2. RISC Architectures
  3. ARM

Exceptions, Interrupts, & Vector Table

  • Exceptions

    • processor sets PC to specific memory address

      • Address is within a special range called vector table

      • Entries in Vector Table are instructions that branch to specific routines for handling particular interrupts/exceptions

    • 0x00000000 is reserved for vector table

      • some processors allow higher address 0xffff0000

      • Linux and windows use this higher address

  • Each vector table entry contains a form of branch instruction pointing to specific routine

    • reset vector: location of first instruction executed by processor when power is applied.

      • branches to initialized code

    • undefined instruction vector: used when processor cannot decode an instruction

    • software interrupt vector: called when an SWI instruction is executed

      • often used to invoke an OS routine

    • prefetch abort vector: used when processor attempts to fetch instruction from address w/o correct access permissions

      • abort occurs in decode stage

    • data abort vector: when instruction attempts to access data memory w/o correct access permission

    • Interrupt request vector: external hardware causes interrupt

    • Fast interrupt request vector: same as above, but requiring faster response time

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