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Low Level Computing
  • Operating Systems
    • General Operating Systems
      • OS Structure
      • Main Memory
        • Basic Hardware
        • Address Binding
        • Memory Address Register
      • Booting
        • MBR (Master Boot Record)
        • Global Descriptor Table
      • Direct Memory Access (DMA)
        • DMA
      • Processes
        • Basics
        • Process Scheduling
    • Linux Operating System
      • Linker Scripts
      • Position Independent Code/Executable
      • Relocation
      • Understanding PLT and GOT
    • Windows Operating System
      • Page 1
    • Real-Time Embedded Systems
      • Real-Time Scheduling
        • Cyclic Executive
  • Computer Architecture
    • Architecture Fundamentals
      • Introduction
      • Cache Basics
      • Cache Memory
      • A Few CPU Formulas
    • RISC Architectures
      • ARM
        • ARM Design Philosophy
        • RISC Review
        • Exceptions, Interrupts, & Vector Table
        • ARM Pipelines
        • ARM Registers
        • ARM Branch Instructions
        • ARM CSPR (Instructions)
        • ARM Data Processing Instructions
        • Load/Store Instructions
        • Profiling Cycle Counter
        • Compiler Optimizations
      • RISCV
    • CISC Architectures
    • Cache Coherency
      • Basic Introduction
      • Memory Sequential Consistency
  • Exploits
    • Walkthrough: Return-to-Libc
    • Access Physical Memory
  • Compilers & Runtime Systems
    • Introduction
      • Programming Language Basics
      • Static Scope
    • Syntax Translation
      • Syntax Defined
      • Parsing
    • Algorithms
      • FIRST FOLLOW (Top-Down) Parsing
      • Building a Recursive Descent Parser
      • Construction: Regular Expression -> NFA
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  1. Computer Architecture
  2. RISC Architectures
  3. ARM

ARM CSPR (Instructions)

  • Program Status Register Instructions

    • MRS instruction transfers the contents of either cpsr or spsr into a register

      • Can also transfer in the reverse direction MSR

    • Allows read/write of cpsr and spsr

    • syntax includes 'fields' which can be a combination of control (c), extension (x), status (s), and flags (f)

    PSR byte regions

    • Control [0:7] bits 0 to 7

      • mode [0:4]

      • T (THUMB ISA) bit 5

      • F (FIQ Interrupts) bit 6

      • I (IRQ Interrupts) bit 7

    • eXtension[8:15]

    • status[16:23]

    • Flags[24:31]

      • V bit 28

      • C bit 29

      • Z bit 30

      • N bit 31

    • Syntax:

      MRS{} Rd, <cpsr|spsr> MSR{} <cpsr|spsr>, Rm MSR{} <cpsr|spsr>, #immediate

  • Example:

    Before: cpsr = nzcvqIFt_SVC

    MRS r1, cpsr BIC r1, r1, #0x80 MSR cpsr_c, r1

    1. Copies the cpsr register to r1

    2. BIC instruction clears bit 7 of r1

    3. Copies r1 back to cpsr

    ** bit 7 is the IRQ, clearing it unmasks IRQ interrupts **

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