Maurice's Notes
Blog
Low Level Computing
Low Level Computing
  • Operating Systems
    • General Operating Systems
      • OS Structure
      • Main Memory
        • Basic Hardware
        • Address Binding
        • Memory Address Register
      • Booting
        • MBR (Master Boot Record)
        • Global Descriptor Table
      • Direct Memory Access (DMA)
        • DMA
      • Processes
        • Basics
        • Process Scheduling
    • Linux Operating System
      • Linker Scripts
      • Position Independent Code/Executable
      • Relocation
      • Understanding PLT and GOT
    • Windows Operating System
      • Page 1
    • Real-Time Embedded Systems
      • Real-Time Scheduling
        • Cyclic Executive
  • Computer Architecture
    • Architecture Fundamentals
      • Introduction
      • Cache Basics
      • Cache Memory
      • A Few CPU Formulas
    • RISC Architectures
      • ARM
        • ARM Design Philosophy
        • RISC Review
        • Exceptions, Interrupts, & Vector Table
        • ARM Pipelines
        • ARM Registers
        • ARM Branch Instructions
        • ARM CSPR (Instructions)
        • ARM Data Processing Instructions
        • Load/Store Instructions
        • Profiling Cycle Counter
        • Compiler Optimizations
      • RISCV
    • CISC Architectures
    • Cache Coherency
      • Basic Introduction
      • Memory Sequential Consistency
  • Exploits
    • Walkthrough: Return-to-Libc
    • Access Physical Memory
  • Compilers & Runtime Systems
    • Introduction
      • Programming Language Basics
      • Static Scope
    • Syntax Translation
      • Syntax Defined
      • Parsing
    • Algorithms
      • FIRST FOLLOW (Top-Down) Parsing
      • Building a Recursive Descent Parser
      • Construction: Regular Expression -> NFA
Powered by GitBook
On this page

Was this helpful?

  1. Computer Architecture
  2. Architecture Fundamentals

A Few CPU Formulas

CPU execution time = (CPU clock Cycles + Memory Stall Cycles) X Clock Cycle Time

- This equation assumes that the CPU clock cycles include the time to handle a cache

hit and that the processor is stalled during a cache miss

Memory Stall cycles = Number of misses X Miss Penalty = IC X Misses/Instruction X Miss penalty = IC X Memory Accesses/Instruction X Miss Rate X Miss Penalty

  • Measuring Instruction count for speculative processors, we only count instructions that commit

  • Measuring memory references is similarly easy

    • Every instruction requires instruction access, and it is easy to decide if it also requires data access.

  • The component miss rate is simply the fraction of cache accesses that result in a miss.

    • Miss rates can be measured with cache simulators that take an address trace of the instruction and data references, simulate the cache behavior to determine which references hit and which miss, and then report the hit-and-miss totals.

    • Many microprocessors today provide hardware to count the number of misses and memory references, which is a much easier and faster way to measure miss rate.

Memory stall clock cycles = IC X Reads per instruction X Read miss rate X Read miss penalty.

  • IC Writes per instruction X Write miss rate X Write miss penalty.

PreviousCache MemoryNextRISC Architectures

Last updated 1 year ago

Was this helpful?