ARM Pipelines

• Three pipeline stages

  • Fetch

  • Decode

  • Execute

• Pipeline allows the core to execute instructions every cycle

  • filling the pipeline is moving instructions into stage

    • in RISC-V 'issuing' is the process of moving values from one stage to the pipeline stage register.

• ARM9 and ARM10 increased the length of the pipeline

  • ARM9: 5 pipeline stages (fetch, decode, execute, memory, write)

  • ARM10: 6 pipeline stages (fetch, issue, decode, execute, memory, write)

• As pipeline length increases (e.g. from 3 stages to 5 or 6), the amount of work done at each stage is reduced

  • increases performance allowing the processor to attain a higher operating frequency

• System latency increases because of cycles required to fill pipeline before the core can execute an instruction.

  • In a 3 stage pipeline, it takes 3 cycles for the first instruction to reach the end of pipeline

  • In a 5, it takes 5. If six, it will take 6

• Increased length can also introduce data (and name) dependencies

  • this can be resolved by writing code using instruction scheduling

    • see chapter 6.