Maurice's Notes
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Low Level Computing
Low Level Computing
  • Operating Systems
    • General Operating Systems
      • OS Structure
      • Main Memory
        • Basic Hardware
        • Address Binding
        • Memory Address Register
      • Booting
        • MBR (Master Boot Record)
        • Global Descriptor Table
      • Direct Memory Access (DMA)
        • DMA
      • Processes
        • Basics
        • Process Scheduling
    • Linux Operating System
      • Linker Scripts
      • Position Independent Code/Executable
      • Relocation
      • Understanding PLT and GOT
    • Windows Operating System
      • Page 1
    • Real-Time Embedded Systems
      • Real-Time Scheduling
        • Cyclic Executive
  • Computer Architecture
    • Architecture Fundamentals
      • Introduction
      • Cache Basics
      • Cache Memory
      • A Few CPU Formulas
    • RISC Architectures
      • ARM
        • ARM Design Philosophy
        • RISC Review
        • Exceptions, Interrupts, & Vector Table
        • ARM Pipelines
        • ARM Registers
        • ARM Branch Instructions
        • ARM CSPR (Instructions)
        • ARM Data Processing Instructions
        • Load/Store Instructions
        • Profiling Cycle Counter
        • Compiler Optimizations
      • RISCV
    • CISC Architectures
    • Cache Coherency
      • Basic Introduction
      • Memory Sequential Consistency
  • Exploits
    • Walkthrough: Return-to-Libc
    • Access Physical Memory
  • Compilers & Runtime Systems
    • Introduction
      • Programming Language Basics
      • Static Scope
    • Syntax Translation
      • Syntax Defined
      • Parsing
    • Algorithms
      • FIRST FOLLOW (Top-Down) Parsing
      • Building a Recursive Descent Parser
      • Construction: Regular Expression -> NFA
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  1. Computer Architecture
  2. RISC Architectures
  3. ARM

ARM Pipelines

  • Three pipeline stages

    • Fetch

    • Decode

    • Execute

  • Pipeline allows the core to execute instructions every cycle

    • filling the pipeline is moving instructions into stage

      • in RISC-V 'issuing' is the process of moving values from one stage to the pipeline stage register.

  • ARM9 and ARM10 increased the length of the pipeline

    • ARM9: 5 pipeline stages (fetch, decode, execute, memory, write)

    • ARM10: 6 pipeline stages (fetch, issue, decode, execute, memory, write)

  • As pipeline length increases (e.g. from 3 stages to 5 or 6), the amount of work done at each stage is reduced

    • increases performance allowing the processor to attain a higher operating frequency

  • System latency increases because of cycles required to fill pipeline before the core can execute an instruction.

    • In a 3 stage pipeline, it takes 3 cycles for the first instruction to reach the end of pipeline

    • In a 5, it takes 5. If six, it will take 6

  • Increased length can also introduce data (and name) dependencies

    • this can be resolved by writing code using instruction scheduling

      • see chapter 6.

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